A hardware scheduler for parallel processing in control

    Student thesis: Doctor of Philosophy

    Abstract

    Parallel processing has been seen as a way to increase computing throughput and has been used at every level in the design of computing machines. In addition, the field of control systems now relies heavily on digital computers to implement new and sophisticated control schemes, to such an extent that single processors are not powerful enough to deliver the required performance.
    The thesis reviews the application of parallelism in computing systems and assesses how parallelism at different levels in a system impact the programming architecture. One parallel system organization, the processor farm has been implemented and is considered as a platform for the execution of control algorithms. Custom hardware based on the concept of a Content Addressable Memory has been designed to eliminate the overhead of traversing a task graph and scheduling the tasks onto the farm. Benchmarks are given showing the effect it has on system performance.
    The results, while proving the efficacy of the hardware, reveal that the elimination of one overhead does not greatly help the overall system performance. This is due to several factors; scheduling anomalies and communication overhead being chief among these. In conclusion, therefore, further work is suggested to alleviate more of the overheads and reduce the likelihood of scheduling problems.
    Date of AwardOct 1998
    Original languageEnglish
    Awarding Institution
    • University of Wales, Bangor
    SupervisorDewi Jones (Supervisor)

    Cite this

    '