FPGA techniques for algorithm acceleration

Abstract

The techniques necessary for the hardware implementation of systems which
would traditionally be implemented in software are investigated, with regard to
two systems: an image processor and an electronic neuron model. The latter is
developed in detail and it is shown that a simplified and space-efficient model can
perform the functions of more complex models. Interesting results are shown and
novel methods of building with these models are demonstrated.

Date of Award	Oct 2007
Original language	English
Awarding Institution	University of Wales, Bangor
Supervisor	Iestyn Pierce (Supervisor)