TY - CONF

T1 - Low-voltage organic memory transistors

AU - Ashall, D.T.

AU - Ashall, D.

AU - Fakher, S.J.

AU - Mabrook, M.F.

PY - 2011/8/15

Y1 - 2011/8/15

N2 - The electrical behavior of an organic memory device based on a pentacene thin film metal-insulator-semiconductor (MIS) and transistor structures incorporating a layer of thermally evaporated metallic floating gate is demonstrated. The devices have been realised using thermally evaporated pentacene (semiconductor) and spin-coated polymethylmethacrylate (PMMA) (insulator). The drain and source electrodes have been fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm evaporated aluminium on a clean glass substrate. The devices containing the floating gate exhibited clear hysteresis in their electrical characteristics (output and transfer characteristics for transistors and also capacitance-voltage (C-V) characteristics of MIS structures). Under an appropriate gate bias (2s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 1 V resulted in a clear write and erase states. The hysteresis in C-V characteristics and shifts in the threshold voltage of the transfer characteristics were attributed to the charging and discharging of the floating gate. The detailed programming and erasing procedures are reported.

AB - The electrical behavior of an organic memory device based on a pentacene thin film metal-insulator-semiconductor (MIS) and transistor structures incorporating a layer of thermally evaporated metallic floating gate is demonstrated. The devices have been realised using thermally evaporated pentacene (semiconductor) and spin-coated polymethylmethacrylate (PMMA) (insulator). The drain and source electrodes have been fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm evaporated aluminium on a clean glass substrate. The devices containing the floating gate exhibited clear hysteresis in their electrical characteristics (output and transfer characteristics for transistors and also capacitance-voltage (C-V) characteristics of MIS structures). Under an appropriate gate bias (2s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 1 V resulted in a clear write and erase states. The hysteresis in C-V characteristics and shifts in the threshold voltage of the transfer characteristics were attributed to the charging and discharging of the floating gate. The detailed programming and erasing procedures are reported.

U2 - 10.1109/NANO.2011.6144538

DO - 10.1109/NANO.2011.6144538

M3 - Paper

SP - 1693

EP - 1698

T2 - Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference, Portland OR., 15-18 August, 2011

Y2 - 3 January 0001

ER -