Development of Frequency-Fixed All-Pass Filter based Single-Phase Phase-Locked Loop

Allbwn ymchwil: Cyfraniad at gyfnodolynErthygladolygiad gan gymheiriaid

Fersiynau electronig

Dogfennau

Dangosydd eitem ddigidol (DOI)

—Phase-locked loops (PLL) are widely used in the
synchronization of grid interfaced power converters. One solution is based on orthogonal signal generation (OSG), which
requires the grid frequency information for their appropriate
operation.This paper developed a new solution to achieve the
PLL function for single-phase grid interconnection but eradicate
additional frequency feedback loops in the traditional architecture of all-pass filter PLL (APF-PLL). Four new topologies are
developed along with their small-signal modeling and dynamic
analysis. A thorough comparison among them on their dynamic
response, steady state accuracy, implementation, and disturbance
rejection capability are carried out. Finally, the best approach
of frequency-fixed APF-PLL is experimentally evaluated with
frequency adaptive APF-PLL and frequency-fixed PLLs belonging to time-delay (TD), and second-order generalized intergrator
(SOGI) families.
Iaith wreiddiolSaesneg
Cyfnodolyn IEEE Journal of Emerging and Selected Topics in Power Electronics
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - 31 Mai 2021

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