TY - JOUR

T1 - High capacity organic memory structures based on PVP as the insulating layer

AU - Mabrook, Mohammed

AU - Fakher, Sundes

AU - Alias, Maysoon

AU - Sayers, Paul

PY - 2018/10/1

Y1 - 2018/10/1

N2 - The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol (PVP) as the gate dielectric are reported in this work. Metal–insulator–semiconductor (MIS) and thin film transistor (TFT) structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V) for MIS structures as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and –40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

AB - The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol (PVP) as the gate dielectric are reported in this work. Metal–insulator–semiconductor (MIS) and thin film transistor (TFT) structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V) for MIS structures as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and –40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

KW - Organic Memory, PVP, AuNPs, Floating-Gate, Organic Thin Film Transistor

U2 - 10.1007/s10854-018-9868-4

DO - 10.1007/s10854-018-9868-4

M3 - Article

SP - 17644

EP - 17650

JO - Journal of Materials Science: Materials in Electronics

JF - Journal of Materials Science: Materials in Electronics

SN - 0957-4522

IS - 20

ER -