TY - JOUR

T1 - Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

AU - Mabrook, Mohammed

AU - Fakher, Sundes

AU - Nejm, Razan

AU - Ayesh, Ahmad

AU - AL-Ghaferi, Amal

AU - Zeze, Dagou

PY - 2016/9/2

Y1 - 2016/9/2

N2 - The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs), metal–insulator–semiconductor (MIS) and thin film transistor (TFT) structures, using poly(methyl methacrylate) (PMMA) as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of SWCNTs, embedded within the insulating layer, were used as the floating gate. SWCNTs-based memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V) for MIS structures, as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics, the shifts in the threshold voltage of the transfer characteristics, and the flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the SWCNTs floating gate. Under an appropriate gate bias (1 s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses as low as 1 V resulted in clear write and erase states

AB - The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs), metal–insulator–semiconductor (MIS) and thin film transistor (TFT) structures, using poly(methyl methacrylate) (PMMA) as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of SWCNTs, embedded within the insulating layer, were used as the floating gate. SWCNTs-based memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V) for MIS structures, as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics, the shifts in the threshold voltage of the transfer characteristics, and the flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the SWCNTs floating gate. Under an appropriate gate bias (1 s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses as low as 1 V resulted in clear write and erase states

U2 - 10.3390/molecules21091166

DO - 10.3390/molecules21091166

M3 - Article

VL - 21

SP - 1166

JO - Molecules

JF - Molecules

SN - 1420-3049

IS - 9

ER -