This thesis focuses on the development of transparent and flexible components such as silver nanowire (AgNW) based transparent conducting electrodes (TCEs) and metal oxide thin film transistors (TFTs) with the aim of improving the stability and performance under real-world conditions. The electrical and environmental stability of these components is, therefore, investigated. For AgNWs a 3-step post processing method was used to enhance the electrical, surface properties of AgNWs TCEs. Thermal embossing process parameters were optimised using a Taguchi orthogonal array, where pressure, time and temperature of the embossing step were all varied. An in-depth study of the effect of thermal embossing, effect of N2 plasma treatment and photonic sintering on the AgNW TCE properties was undertaken. X-ray photoelectron spectroscopy, atomic force microscopy and scanning electron microscopy analysis of AgNW TCEs revealed several mechanisms responsible for the reduction of sheet resistance and surface roughness. However, transmittance and haze remained unchanged after post processing of TCEs. Electrical and environmental stability of AgNW TCEs is investigated through accelerated lifetime testing (ALT) and method to enhance stability of AgNW TCEs are developed.
A Plackett-Burman design was applied to optimise the production of anodised (Al2O3) dielectric films for ZnO thin film transistor (TFTs). A comprehensive study of the effect of the processing parameters on the performance of anodized Al2O3 gate dielectric films for ZnO TFTs is conducted. The impact of the process factors on the overall performance of the ZnO TFTs is also investigated. The development of low voltage metal oxide TFTs based upon ZnO and flexible IGZO is reported using Al2O3 as the gate dielectric. The performance of transparent IGZO TFTs base on AgNW and ITO gate electrode is also studied.
Understanding the origin of electrical instability in inorganic metal oxide TFTs over long periods is also essential to realize high performance circuits. In this thesis, the effects of positive gate bias stress (PGBS) on IGZO TFTs are also investigated. It was found that the threshold voltage, VT, always shifted in the direction of the applied gate voltage. It was also observed that the threshold voltage shift, ∆VT, is reduced with CYTOP passivation and white light illumination. A density of states (DoS) analysis is carried out during PGBS to confirm the origin of trap states due to bias stressing.