Gold nanoparticles as a floating gate in Pentacene/PVP based MIS memory devices

Research output: Contribution to conferencePaper

Electronic versions

We report on the fabrication and characterization of a pentacene and poly(4-vinyl phenol) (PVP) based metal-insulator-semiconductor (MIS) memory structures. The surface morphology of pentacene grown on a thin layer of PVP showed the largest polycrystalline grains as compared to other dielectric materials such as polymethyl-metacrylate (PMMA) or SU8. The effect of larger grain size of pentacene was reflected in the capacitance-voltage (C-V) characteristics of the devices, where devices with larger pentacene grains showed lower operating voltages and a steeper slope of the depletion region of the C-V curve. The introduction of solution-processed gold nanoparticles (AuNPs) embedded within the PVP layer induced the memory characteristics as it served as a floating gate in the MIS Al/PVP/AuNPs/PVP/Pentacene/Au structure. The C-V characteristics of the memory devices exhibit a clockwise hysteresis due to the charging and discharging of AuNPs from the aluminium gate through the PVP insulator layer. A memory window of 8.5V was achieved at a ±10V voltage sweep range; wider memory windows were achieved at higher voltage sweep ranges. The memory devices have hysteresis centred close to 0V and a short depletion region which make it favourable for low voltage and fast operation in organic and flexible electronics applications.
Original languageEnglish
Pages1-5
DOIs
Publication statusPublished - 20 Aug 2012
Event12th IEEE Conference on Nanotechnology : IEEE-NANO - Birmingham, United Kingdom
Duration: 20 Aug 201323 Aug 2013
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6310163

Conference

Conference12th IEEE Conference on Nanotechnology
Abbreviated titleIEEE-NANO
Country/TerritoryUnited Kingdom
CityBirmingham
Period20/08/1323/08/13
Internet address
View graph of relations